 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 1 - AK7712a-vt built-in 20-bit adc/dac sophisticated audio dsp general description the AK7712a is a dsp(digital signal processor) with built-in high performance 20bit 2ch adc and 4ch dac, on purposeto control the sound field. it is possible to calculate 383 steps on 44.1khz and 48khz sampling respectively. in case of 32khz sampling, it can caluculate up to 511 steps. with a combination of this lsi and external memory for delay data,it can berealized easily to control the sound field such as echo, surround presence controller, and key-control which are needed forsomething like karaoke. parametric equalizing can be done without external memory. features [ dsp unit ] ? word length: 24-bit (data ram) ? instruction cycle time: 54ns(maximum speed) ? multiplier: 24 16 ? 40-bit ? divider: 16 ? 16 ? 16-bit ? program ram: 384 32 bit ? external memory: dram,pseudo-sram and sram can be connected (only use for delay data). ? sampling frequency: 32khz ~ 48khz ? automatic clear function of external ram: 47msec after bringing rst high at fs=48khz (include internal data ram) ? microcomputer interface: synchronized signal type 8-bit serial input 1 channel, synchronized signal type 24-bit serial output 1 channel ? master clock: 512(511)/384(383)/256(255)fs the value inside ( ) is maximum calculation steps. 512fs mode is available when 32khz sampling is chosen. ? conversion of master/slave mode for lrck and bclk: when master mode is selected, the outputs of lrck and bclk depend on the set-up for input format. ? serial input ports(2 ~ 4ch), and output ports(2 ~ 6ch) : 16/20/24 bit words [ adc unit ] ? 20-bit 64 oversampling ds adc: 2ch ? s/(n+d): 92db ? dr, s/n: 98db [ dac unit ] ? 20-bit 128 oversampling ds dac: 4ch ? s/(n+d): 86db ? dr, s/n: 97db ? digital hpf (fc=1hz) [ total ] ? power supply: +5v ? package: 100pin lqfp(0.5mm pitch)
asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 2 - detail features 1) calculate unit multiplication: 24-bit 16-bit ? 40-bit(fixed-point, 2 instruction cycle time) division: 16-bit ? 16-bit ? 16-bit(fixed-point, 17 instruction cycle time) alu: 34-bit arithmetic operation 24-bit arithmetic logic operation shift: 1-,2-,3-,4-,6-,8-,15-bit right/left shift AK7712a has indirect shift function. (a shift using dbus data can not use dbus as multiplication input.) register: 34-bit 4(acc) [for alu] 24-bit 8(tmp) [for dbus connection] double precision operation: 24-bit(data) 31-bit(coefficient), 45 31, 45 16 2) internal memory program ram: 384 word 32-bit data ram: 128 word 24-bit coefficient ram: 256 word 16-bit offset ram: 40 word 16-bit (for external memory access) microcomputer buffer: 16 word 16-bit 3) external memory access (sram pseudo-sram dram) objective memory: 256k(32k 8-bit),1m(128k 8-bit) 1 / sram 256k(32k 8-bit),1m(128k 8-bit) 1 / pseudo-sram 256k(64k 4-bit),1m(256k 4-bit) 2 or 1 / dram (half volume of 1m dram is used as 512k memory.) treating bit length: 16-bit (24-bit is available, but double time is needed for access.) the number of times to access: sram, 256k pseudo-sram ; 76 at 384fs : dram, 1m pseudo-sram ; 64 at 384fs (32 at one dram) : sram, 256k pseudo-sram ; 51 at 256fs : dram, 1m pseudo-sram ; 42 at 256fs (21 at one dram) memory access time: less than 100nsec maximum address length: 65535 sampling times (at 1m sram) 2.048sec at 32khz, 1.486sec at 44.1khz, 1.365sec at 48khz 4) input/output port input: 2ch analog input: 20-bit adc, dr=98db (16-bit at bclk=32fs) [when built-in adc is connected.] 2ch digital input: msb justified 20-bit (16bit at bclk=32fs) ? msb first serial input [when built-in adc is isolated.] 2ch digital input: msb justified 16- 24-bit / lsb justified 16- 24-bit ? msb first serial input output: 4ch analog output: 20-bit dac, dr=97db(16-bit at bclk=32fs) [when built-in adc is connected.] 4ch digital output: msb justified 20-bit (16bit at bclk=32fs) ? msb first serial output [when built-in adc is isolated.] 2ch digital output: msb justified 16- 24-bit/ lsb justified 16-bit ? msb first serial output 5) cascade connection with this lsi is possible. 6) interface to microcomputer: synchronized 8-bit serial input / synchronized 24-bit serial output 7) calculation cycle: max 18.432mhz(54nsec) [at 48.0khz, 384fs, 5v] 8) master/slave conversion of lrck bclk is possible. 9) bclk: 32fs/48fs/64fs (64fs only at master mode) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 3 - ? ? ? ? AK7712a block diagram 1) adc,dac inside connection mode (opcl: l) AK7712a block diagram note: please use sdin2,sdda and sdda2 with "l" or open. sdad,sdout2 and sdout3 output "l". asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 4 - 2) adc,dac outside connection mode (built-in adc,dac isolation mode) (opcl:h) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 5 - ? ? ? ? AK7712a dsp unit block diagram data address cp0,1 dp0,1 d0 a 7 ad0 a 16 cram 256 16 dram 128 24 delay data 16-bit ext ram control ofram 40 16 cbus (16-bit) dbus (24-bit) mpx16 mpx24 microcomputer serial micom i/f control interface d e c pram 384 32 x y multiply 16 24 ? 40 24-bit 40-bit pc stack:1level 34-bit mul dbus shift tmp 8 24-bit 34-bit sdin1 (24/16-bit) 2 24/16-bit msb/lsb justified serial in sdin2 (20/16-bit) 2 20/16-bit msb justified serial in (note 1) a b alu 34-bit overflow margin:4bit sdout1 (24/16-bit) 2 24/16-bit msb/lsb justified serial out dr0 a 3 sdout2 (20/16-bit) 2 20/16-bit msb justified serial out (note 2) 24-bit sdout3 (20/16-bit) 2 20/16-bi msb justified serial out (note 3) overflow data generator note 1: normally it's connected to built-in adc 2: normally it's connected to built-in dac1 peak detector 3: normally it's connected to built-in dac2 division 16 ? 16 ? 16 asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 6 - ? ? ? ? ordering guide AK7712a-vt -40 ~ +85 c 100pin lqfp akd7712a evaluation board ? ? ? ? pin layout asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 7 - pin / function ? ? ? ? power supply pin no. pin name i/o function 24, 32, 50, 70, 73 dvdd - digital power supply 25, 31, 49, 69, 72 dvss - digital ground 87, 97 avdd - analog power supply 86, 96 avss - analog ground 79, 99 avb - analog substrate power supply 10, 11, 74, 75 dvb - digital substrate power supply ? ? ? ? external ram interface signal pin no. pin name i/o function 41 ~ 48, 51 ~ 59 a16 ~ a0 o address output for external ram (a0:lsb justified, a16:msb justified) 40 we o write signal output for external sram/ pseudo-sram/ dram 39 resce o ras for external dram / pseudo-sram-ce 38 casrf o cas for external dram / pseudo-sram refresh 61 ~ 68 io0 ~ io7 i/o data input/output for external ram 60 oe o output enable signal output for external sram/ pseudo-sram/ dram asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 8 - ? ? ? ? microcomputer interface signal, controls signal, input/output data, reset, etc. pin no. pin name i/o function 30 wrq i command register reset input for microcomputer interface 33 sclk i clock input for serial data input for microcomputer interface 36 drdy o output data ready output for microcomputer interface 34 si i serial data input for microcomputer interface 37 so o serial data output for microcomputer interface (hi-z state at cs="h") 35 wrdy o data write ready output for microcomputer interface (hi-z state at cs="h") 29 cs i chip select input for microcomputer interface asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 9 - ? ? ? ? AK7712a control signal, input/output data signal, reset, etc. pin no pin name i/o function 6 rst i reset input ("l" reset) (note 1) 5 pd i power down (note 1) 3 pdad i ad reset control (note 1) 4 pdda i da reset control (note 1) 19 sdin1 i serial data input 1 msb justified 16- 24-bit / lsb justified 16- 24-bit 18 sdout1 o serial data output 1 msb justified 16- 24-bit / lsb justified 16-bit 12 sdin2 i serial data input 2 (opcl : "h" ) (note 2) msb justified 16- 20-bi 13 sdad o serial data output 2 (opcl : "h" ) (note 3) msb justified 16- 20-bit, common set-up with sdin2 15 sdda i serial data input 3 (opcl : "h" ) (note 2) msb justified 16- 20-bit, common set-up with sdout2 14 sdout2 o serial data output 3 (opcl : "h" ) (note 3) msb justified 16- 20-bit 16 sdda2 i serial data input 4 (opcl : "h" ) (note 2) msb justified 20-bit (16-bit at bclk=32fs ) 17 sdout3 o serial data output 4 (opcl : "h") (note 3) msb justified 20-bit (16-bit at bclk=32fs) 21 bclk i/o clock input/output for serial data input 22 lrck i/o l/r channel identify signal input/output 20 smode i interface clock select input/output set-up for each clock pin of lrck and bclk "l":slave mode(21,22 input), "h":master mode(output) 23 clko o master clock output (note 4) 27 xto o output for quartz oscillator when an external clock is input, this pin should be left floating. 26 xti i input for quartz oscillator a crystal can be connected between this pin and xto, or an external cmos clock can be input on this pin. note:1 about the directions, please refer the paragraph of power down reset control on p.65. 2 set to "l" or "open" when opcl is "l". 3 the output is "l" when opcl is "l". 4 during a timing of changing control register, clko is instability. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 10 - ? ? ? ? analog relational pins pin no. pin name i/o function 93 ainl+ i adc lch analog non-inverted input 92 ainl- i adc lch analog inverted input 91 ainr+ i adc rch analog non-inverted input 90 ainr- i adc rch analog inverted input 84 aoutl1 o dac1 lch analog output 1 83 aoutr1 o dac1 rch analog output 1 81 aoutl2 o dac2 lch analog output 2 80 aoutr2 o dac2 rch analog output 2 85 vrdal i standard voltage input of dac unit (normally connected to analog ground) 88 vrdah i standard voltage input of dac unit (normally connected to 87 pin. 0.1u and 10uf capacitor are connected between this pin and vrdal pin.) 95 vradl i standard voltage input of adc unit (normally connected to analog ground) 98 vradh i standard voltage input of adc unit (normally connected to 97 pin. 0.1u and 10uf capacitor are connected between this pin and vradl pin.) 94 vcom o common voltage (0.1u and 10uf capacitor are connected between this pin and analog ground.) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 11 - ? ? ? ? test pin, etc. pin no. pin name i/o function 77 dzf1 o zero input find (for dac1) 76 dzf2 o zero input find (for dac2) 1 tsti1 i test input 1 ; use as "l" or open 28 tsti2 i "l": clko(23pin) output "h": clko(23pin) ? "l" 7 tstio1 i/o test input 1 ; use as "l" or open 8 tstio2 i/o test input 2 ; use as "l" or open 9 tstio3 i/o test input 3 ; use as "l" or open 2 opcl i adc,dac connection choice "l": connect , "h": separate 71 dzfset i zero point find set "h": dzf output , "l": dzf output ? "l" 78, 82, 89, 100 nc - nc pins do not be bonded inside. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 12 - absolute maximum ratings (avss,dvss=0v; note 1) parameter symbol min max unit dc power supply: analog power digital power(dvdd) (note 2) substrate power(avb,dvb) va vd vb -0.3 -0.3 -0.3 6.0 (vb)+0.3 6.0 v v v input current (except power supply) iin - 10 ma analog input voltage ainl+,ainl-,ainr+,ainr-,vref vina -0.3 (va)+0.3 v digital input voltage (note 2) vind -0.3 (vb)+0.3 v ambient temperature ta -40 85 c storage temperature tstg -65 150 c note 1: all the value mean the voltage against the ground pin. 2: maximum absolute value must be within 6.0v, i.e. vb+0.3v 6.0v. warning: to operate beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss,dvss=0v; note 1) parameter symbol min typ max unit power supply: analog power digital power (dvdd) substrate power (avb,dvb) va vd vb 4.75 4.75 4.75 5.0 5.0 5.0 5.25 vb 5.25 v v v (note 2,3,4) note 1: all the value mean the voltage against the ground pin. 2: the va and vb should be powered at the same time or earlier than vd. 3: the va and vb are connected together through the chip substrate and has several ohms resistors. the va and vb should be supplied from the same power unit. 4: analog input/output voltages are proportional to the voltages of vradh,vrdah. * akm assumes no responsibility for the usage beyond the conditions in this data sheet. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 13 - analog characteristics (ta=25 c; avdd,dvdd,avb,dvb=5.0v; vradh=avdd,vradl=avss,vrdah=avdd,vrdal=avss; fs=44.1khz; bclk=64fs master mode; mclk=256fs; input signal frequency=1khz; 20-bit; measurement band width=10hz ~ 20khz; dsp unit is reset; adc differential input; unless otherwise specified.) parameter min typ max units adc unit : resolution 20 bits dynamic characteristics s/(n+d) ( -0.5db ) 86 92 db s/n (a-weight) 94 98 db dynamic range (a-weight) (note 1) 94 98 db interchannel isolation (f=1khz) 90 105 db dc accuracy interchannel gain mismatch 0.1 0.3 db gain drift - 50 - ppm/ c analog input input voltage (note 2) 1.9 2.0 2.1 vp-p input impedance 220 k w dac unit : resolution 20 bits dynamic characteristics s/(n+d) ( 0 db ) 80 86 db s/n (a-weight) 93 97 db dynamic range (a-weight) (note 1) 93 97 db interchannel isolation (f=1khz) (note 4) 90 105 db dc accuracy interchannel gain mismatch (note 4) 0.2 0.5 db gain drift - 50 - ppm/ c analog output output voltage (note 3) 2.65 2.90 3.15 vp-p load resistance 5 k w note 1: s/(n+d) with an input signal of -60db below full-scale. 2: the full-scale of analog input voltage(ain = (ain+) - (ain-) ) equals to fs = (vradh - vradl) 0.4 3: the full-scale of output voltage(0db) is proportional to vrdah. aout(typ. @0db) = 2.9vpp vrdah/5 4: between l channel and r channel of each dac. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 14 - digital filter characteristics this data is not the guaranteed characteristic value but the designed value as a reference. adc unit : (ta=25 c; va,vd,vb=5.0v 5%; fs=44.1khz) parameter symbol min typ max units passband ( 0.06db) ( -6.0 db) (note 1) pb 0 0 20.00 22.05 khz khz stopband (note 1) sb 24.35 khz passband ripple (note 2) pr 0.005 db stopband attenuation (note 3,4) sr 80 db group delay distortion d gd 0us group delay (ts=1/fs) gd 29.3 ts note 1: the frequencies of passband/stopband are proportional to the sampling frequency (fs). 2: passband is dc to 19.75khz at fs=44.1khz. 3: stopband is 27.56khz to 2.795mhz at fs=44.1khz. 4: the analog modulator samples the input at 2.8224mhz for fs=44.1khz. there is no rejection of input signals at those band width which are multiples of the sampling frequency(n x 2.8224mhz 20.21khz; n=0,1,2,3 ? ). dac unit : (ta=25 c; va,vd,vb=5.0v 5%; fs=44.1khz;) parameter symbol min typ max units digital filter passband ( -0.2 db) (note 1) ( -6.0 db) pb 0 - 22.05 20.0 - khz khz stopband (note 1) sb 24.3 khz passband ripple pr 0.05 db stopband attenuation sa 41 db group delay (ts = 1/fs) (note 2) gd - 14.7 - ts digital filter + analog filter amplitude characteristics 0 ~ 20khz - 0.5 - db note 1: the frequencies of passband/stopband are proportional to the sampling frequency (fs); pb=0.4535fs(@-0.2db), sb=0.546fs(@-41db). 2: the calculating delay time is occurred by digital filtering. this is the time from the setting 20-bit data on input register to the output of analog signal. (at fs=44.1khz) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 15 - dc characteristics (avdd=dvdd; avd,dvb=5.0v 5%; ta=25 c) parameter symbol min typ max units high level input voltage low level input voltage high level input voltage iout=-20ua low level input voltage iout= 20ua input leak current (note 1) input leak current (note 2) (pull-down pin) vih vil voh vol iin iid 70%vdd - vdd-0.1 - - - - - - - - 100 - 30%vdd - 0.1 10 - v v v v ua ua note 1: except pull-up/pull-down pin 2: pull-down pin(typ 50k w ) is as follows; pdad, pdda,sdin2,sdda,sdda2,tsti1,tsti2, tsto1,tsto2,tsto3,opcl pin. (ta=25 c; avdd,dvdd,avb,dvb=5.0v; master clock = 18.432mhz, xti=384fs [fs=48khz]; input 1khz full scale sine wave input from 2ch analog input pin of adc and output to 4ch dac.) power supply parameter min typ max units power supply current normal operation (rst=pd="h") avdd + avb + dvb dvdd power-down mode (rst=pd="l") avdd + avb + dvb+ dvdd (note 3) 47 51 20 70 80 250 ma ma ua power dissipation normal operation power-down mode 490 0.1 750 1.25 mw mw note 3: this is the value in the conditions that external clock(xti,bclk,lrck) is "l", sclk is "h". asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 16 - switching characteristics clock (ta=25 c; va,vd,vb=5.0v 5%; c l =20pf) parameter symbol min typ max units control clock frequency master clock quartz oscillator mode 256fs: 384fs: 512fs: external clock mode duty cycle 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high audio serial data clock (bclk) channel select clock (lrck) duty cycle microcomputer serial data clock (sclk pulse width low pulse width high reset timing pd pulse width rst pulse width clock falling time [xti, bick, lrck, sclk] (note) clock rising time [xti, bick, lrck, sclk] (note) f clk f clk f clk f clk t clkl t clkh f clk t clkl t clkh f clk t clkl t clkh f blk f s f slk t slkl t slkh t pd t rst t f t r 8.192 12.288 12.288 40 8.192 30 30 12.288 20 20 12.288 20 20 1.024 32 49 30 30 11.2896 16.9344 16.384 50 11.2986 16.9344 16.384 2.8224 44.1 50 100 100 12.288 18.432 18.432 60 12.288 18.432 18.432 3.072 48 51 12.288 10 10 mhz mhz mhz % mhz ns ns mhz ns ns mhz ns ns mhz khz % mhz ns ns ns ns ns ns note : at input of external cmos clock for xti. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 17 - 1) audio interface timing (avdd=dvdd,avb,dvb=5.0v 5%,ta=25 c; master clock 16.9344mhz,xti=384fs[fs=44.1khz]; cl=20pf) parameter symbol min typ max units slave mode bclk cycle bclk pulse width low pulse width high time from bclk" " to lrck (note 1) delay time from lrck to dout(msb) delay time from bclk" " to dout latch hold time of sdin latch setup time of sdin master mode bclk cycle duty cycle bclk pulse width low pulse width high time from bclk" " to lrck delay time from lrck to dout(msb) delay time from bclk" " to dout latch hold time of sdin latch set up time of sdin t blk t blkl t blkh t blr t lrd t blkd t dinh t dins t blk t blkl t blkh t blr t lrd t blkd t dinh t dins 312.5 100.0 100.0 30-t blkh 40 40 100.0 100.0 -20 40 40 64fs 50 30+t blkl 70 70 20 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 1 : this standard value is provided for not to be overlapped the edge of lrck and bclk" - " each other. 2) microcomputer interface timing (avdd=dvdd,avb,dvb=5.0v 5%,ta=25 c; master clock 16.9344mhz,xti=384fs[fs=44.1khz];cl=20pf) parameter symbol min typ max units from cs" " to wrq" " from rst" " to wrq" " from wrq" - " to cs" - " from wrq" - " to rst" - " from wrq" " to sclk" " from last sclk" - " to wrq" - " sclk cycle sclk pulse width low pulse width high si latch hold time si latch set up time from cs" " to cancellation of so,wrdy "hi-z" (note2) from cs" - " to so,wrdy"hi-z" (note2) from cs" - " to drdy" " from sclk" " to so setup time (note2) t csw t rsw t wrc t wrs t wsc t scw t slk t slkl t slkh t sih t sis t cshr t cshs t csdr t sos 100 100 100 100 100 166(note1) 200 80 80 50 50 100 800 100 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 1 : master clock cycle 3 note 2 : see timing chart. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 18 - 3)read/write interface timing of external ram (avdd,dvdd,avb,dvb=5.0v 5%, ta=25 c, cl=20pf) xti(mhz) 18.432 16.934 12.288 parameter symbol min max min max min max units address delay time from oe " - " (writing) address delay time from oe " " (reading) access time address set-up time data set time data hold time pulse width to write t aoew t aoer t wcy t wd t ds t dh t wp -15 105 10 80 10 60 15 70 -18 115 12 90 12 70 18 80 -20 170 15 135 15 90 20 110 ns ns ns ns ns ns ns 4) refresh interface timing of pseudo sram(external ram) (avdd,dvdd,avb,dvb=5.0v 5%, ta=25 c, cl=20pf) xti(mhz) 18.432 16.934 12.288 parameter symbol min max min max min max units auto refresh cycle pulse width of refresh command delay time of refresh command pre-charge time of refresh t fc t fap t rfd t fp 145 80 100 35 162 90 110 40 210 135 160 60 ns ns ns ns 5) read/write interface timing of pseudo sram(external ram) (static column mode) (avdd,dvdd,avb,dvb=5.0v 5%, ta=25 c, cl=20pf) xti(mhz) 18 .432 16.934 12.288 parameter symbol min max min max min max units address delay time from oe " - " (writing) address delay time from oe " - " (reading) column address hold time sc mode read/write cycle address setup time pulse width of chip enable column address hold time (after write) chip enable time column address setup time pulse width of write command data set time data hold time t aoew t aoer t cah t rsc t as t ce t ahw t cw t asw t wp t dw t dh -15 110 80 10 180 10 95 10 35 50 10 15 70 -18 120 90 12 200 12 105 12 40 60 12 18 80 -20 170 135 15 280 15 140 15 60 90 15 20 110 ns ns ns ns ns ns ns ns ns ns ns ns asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 19 - 6) read/write interface timing of pseudo sram(external ram) (normal mode) (avdd,dvdd,avb,dvb=5.0v 5%, ta=25 c, cl=20pf) xti(mhz) 18.432 16.934 12.288 parameter symbol min max min max min max units address delay time from oe " - " (writing) address delay time from oe " - " (reading) hold time of column address address setup time pulse width of chip enable pre-charge time of chip enable chip enable time pulse width of write command data set time data hold time t aoew t aoer t cah t as t ce t p t cw t wp t dw t dh -15 110 10 90 40 90 35 100 10 15 70 -18 120 12 100 50 100 40 110 12 18 80 -20 170 15 135 60 135 60 160 15 20 110 ns ns ns ns ns ns ns ns ns ns 7) refresh interface timing of dram(external ram) (cas before ras refresh) (avdd,dvdd,avb,dvb=5.0v 5%, ta=25 c, cl=20pf) xti(mhz) 18.432 16.934 12.288 parameter symbol min max min max min max units read cycle pulse width of rasce"h" pulse width of rasce"l" rasce pre-charge casrf hold time casrf setup time at auto refresh casrf hold time at auto refresh t crd t wrh t wrl t rpc t sur t hrrc 240 105 105 80 10 200 260 120 120 90 12 220 360 170 170 130 15 320 ns ns ns ns ns ns 8) read/write interface timing of dram(external ram) (page mode) (avdd,dvdd,avb,dvb=5.0v 5%, ta=25 c, cl=20pf) xti(mhz) 18.432 16.934 12.288 parameter symbol min max min max min max units address delay time fromoe " - " (write) address delay time fromoe " " (read) rasce preceded address setup time rasce followed address hold time casrf preceded address setup time casrf followed address hold time casrf hold time after write write hold time after casrf write pulse width data setup time data hold time after write pulse width of casrf"h" pulse width of casrf"l" t aoew t aoer t sura t hra t suca t hclca t hwch t hclw t w t sud t hwld t wch t wcl -15 10 12 10 45 40 55 40 0 60 22 54 15 70 -18 12 14 12 45 43 65 43 0 70 24 62 18 80 -20 15 18 15 60 60 90 60 0 100 32 90 20 110 ns ns ns ns ns ns ns ns ns ns ns ns ns asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 20 - ? ? ? ? timing waveform asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 21 - asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 22 - asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 23 - read/write interface timing of pseudo sram (static column mode) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 24 - asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 25 - function manual ? ? ? ? dsp unit : execution timing of each command each blocks(pram,dram,cram,calculation unit,etc.) actions on pipeline. on controlling of this pipeline, each stages(command fetch, command decode and execution) are handled in parallel, the operations for each block is executed by 32-bit holizontal code. therefore each operations are executed equivalently in one machine cycle. the following is the executing timing of each command. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 26 - ? ? ? ? calculation function 1) arithmetic system asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 27 - << dbus ? register,etc. >> except for @iorl, take data from msb. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 28 - 2) multiplier multiplier outputs the 31-bit data for shift circuit as a result of fixed-point calculation(24-bit(data) 16-bit(coefficient) = 40-bit). 4 ways of multiplication can operate for the data as follows. the output data is extended from msb for reason that the data overflows at -1 -1. the following combinations are possible for input. 16-bit input 24-bit input notes coefficient ram coefficient ram dbus dbus data ram dbus data ram dbus calculation of x 2 16-bit 24-bit x y partial product carry sum ? input register ? partial product register final adder 40-bit shifter multiplication actions always synchronous with cmck, the product is output in 2 cycles. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 29 - together with shift function, each double-precision calculations of (24 31-bit), (45 31-bit) and (45 16-bit) are available. , (24 31-bit) calculation (24 31-bit) calculation is done with coefficient ram data regulated as follows. the obtained value x yh should be added after shifting 16 bits to left compared with x yl. but, as x yl is the data which is shifted 1bit to right, actually x yh is added after shifting 15 bits to left. ,op, , ,cpu,du1,,, ;read of coefficient(msb) and data ,op, , ,cpu, ,,, ;read of coefficient(lsb) ,op,cr dr , , , ,,, ,op,cr dr , , , ,,, ,op, ,idr0=sh0 << , , ,,, ,op, ,idr0=shrf + ldr0 , , ,,, ;(x yh) + 15-bit right-shifted (x yl) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 30 - this 34-bit data is shifted 15 bits to right and then is added to the upper data. ,op, , ,cpu,du1,, ,;read of coefficient(msb) and data(msb) ,op, , ,op,cr dr , ,op,cr dr , ,op,cr dr ,idr0=sdlf << ,op,cr dr ,idr1=sh0 << ,op,cr dr ,idr0=shr6 + ldr0 ,op, ,idr2=shr6 << ,op, ,idr0=sh0 + ldr0 ,pp, ,idr0=bhrf + ldr0 ,op, , ,pp, ,idr1=bdrf + ldr1 , , ,, ,; , ,du1,, ,;yh xh,read of data(lsb) ,cpu, ,, ,;yh xh,read of coefficient(lsb) , ,dd1,, ,;yh xl(shifted 6bit to right) , , ,, ,;yl xl(shifted 21 to right) , , ,, ,;yl xh , , ,, ,; , , ,, ,; , , ,,odr2 ,; , , ,, ,;odrb: lower 24 bits data , , ,,odrb ,;dr1: upper 24 bits data asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 31 - , (45 16-bit) calculation (45 16-bit) calculation is done with the data regulated as follows. this 34-bit data is shifted 15 bits to right and then is added to upper data. in this way, upper 24 bits and lower 21 bits are calculated. ,op, , ,cpu,du1,, , ;read of coefficient(msb), data(msb) ,op, , ,op,cr dr , ,op,cr dr , ,op,cr dr ,idr0=sdlf << ,op, ,idr1=sh0 << ,op, ,idr0=shr6 + ldr0 ,op, , ,pp, ,idr1=bdrf + ldr1 , , ,, , ; ,cpu, ,, , ;y xh,read of coefficient(lsb) , , ,, , ;y xh , , ,, , ;y xl(shifted 6bit to right) , , ,, , ; , , ,, , ; , , ,, , ;odrb: lower 24 bits data , , ,,odrb, ;dr1: upper 24 bits data asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 32 - 3) shift calculation the shift has two sources of multiplier output and dbus. in the case of shortage of data length, msb side is extended the highest bit, lsb side is put in 0 to output 34-bits data. the shift commands which shift the data 0/1/2/3/4/6/8/15 bits to right/left, and the indirect shift command @shr are prepared. on using the command (bh**) which shift the dbus data, you can use only cram and dram data for multiplication input at the same line. the indirect shift command is carried out in 1 step, taking priority of shift field command. the timing of shift command is showed below. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 33 - sdlf and bdrf take a peculiar action to calculate 45 31 and 45 16. the example program is shown on section 2) multiplier. sdlf shifts the lower 15 bits of the product to 15 bits left, and calculates the 34 bits data, whose upper 13 bits and lower 6 bits are "0". the lower 6 bits of the product are set to "0" at next step. bdrf shifts the 13 bits from upper extended data of dr0 to 15 bits right as input data, and extends this 19-bit data from msb for 15 bits upper, and then calculate 34-bit data, which is set the lower 6 bits to "0". in this command, although not appoint dr register, dr0 data is chose and is added to upper data register. (by hardware, the output of dr0 is directly connected to shift.) a b c d e f 4-bit extension shift to 15 bits right a b c d 0 0 0 0 0 0 lower 6 bits ="0" 15-bit extension of msb (extend from msb of the extended 4 bits) in addition to the direct shift command by the program mentioned above, the indirect shift, which execute with shift number set to indirect shift command circuit, is prepared. the relation of shift and shift number is shown as following colum. this circuit is connected with upper 5 bits of dbus, and is set value by @shr command, and then is carried out in next step, taking priority of shift field command. using this function and peak detection in p.44, the data can be regulated. (ex. 163afe(hex) ? 58ebf8(hex)) the example of program is shown as follows. (assuming that dr0 is regulated.) ,op,, ,,,,odr0 ,@pdr ;detecting size of dr0 ,op,, ,pp,,idr0=bh0 << ,,,,pdr ,@shr ;setting shift number with indirect shift ,,,,odr0 , ;execution of indirect shift taking priority of bh0 after 1 step. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 34 - set value of shift number shift set value of shift number shift 1 0 0 0 0 no shift 0 0 0 0 0 no shift 1 0 0 0 1 1 bit to right 0 0 0 0 1 1 bit to right 1 0 0 1 0 2 bits to right 0 0 0 1 0 2 bits to right 1 0 0 1 1 3 bits to right 0 0 0 1 1 3 bits to right 1 0 1 0 0 4 bits to right 0 0 1 0 0 4 bits to right 1 0 1 0 1 5 bits to right 0 0 1 0 1 5 bits to right 1 0 1 1 0 6 bits to right 0 0 1 1 0 6 bits to right 1 0 1 1 1 7 bits to right 0 0 1 1 1 7 bits to right 1 1 0 0 0 8 bits to right 0 1 0 0 0 8 bits to right 1 1 0 0 1 9 bits to right 0 1 0 0 1 9 bits to right 1 1 0 1 0 10 bits to right 0 1 0 1 0 10 bits to right 1 1 0 1 1 11 bits to right 0 1 0 1 1 11 bits to right 1 1 1 0 0 12 bits to right 0 1 1 0 0 12 bits to right 1 1 1 0 1 13 bits to right 0 1 1 0 1 13 bits to right 1 1 1 1 0 14 bits to right 0 1 1 1 0 14 bits to right 1 1 1 1 1 15 bits to right 0 1 1 1 1 15 bits to right the function of shift is shown as follows. sh0: the product with no shift *bh0 : the dbus data with no shift shr1: the product shifted 1 bit to right *bhr1: the dbus data shifted 1 bit to right shr2: the product shifted 2 bits to right *bhr2: the dbus data shifted 2 bits to right shr3: the product shifted 3 bits to right *bhr3: the dbus data shifted 3 bits to right shr4: the product shifted 4 bits to right *bhr4: the dbus data shifted 4 bits to right shr6: the product shifted 6 bits to right *bhr6: the dbus data shifted 6 bits to right shr8: the product shifted 8 bits to right *bhr8 the dbus data shifted 8 bits to right shrf: the product shifted 15 bits to right *bhrf the dbus data shifted 15 bits to right shl1: the product shifted 1 bit to left *bhl1: the dbus data shifted 1 bit to left shl2: the product shifted 2 bits to left *bhl2: the dbus data shifted 2 bits to left shl3: the product shifted 3 bits to left *bhl3: the dbus data shifted 3 bits to left shl4: the product shifted 4 bits to left *bhl4: the dbus data shifted 4 bits to left shl6: the product shifted 6 bits to left *bhl6: the dbus data shifted 6 bits to left shl8: the product shifted 8 bits to left *bhl8: the dbus data shifted 8 bits to left shlf: the product shifted 15 bits to left *bhlf: the dbus data shifted 15 bits to left #sdlf: the product shifted 15 bits to left *#bdrf: the dbus data shifted 15 bits to left @shr:input the indirect shift value from dbus(5 bits connection from msb) * : the use restriction is exist. (it can use when the input of multiplication is set to cram,dram.) #: special command used at double-precision calculation(45 31, 45 16). asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 35 - 4) alu alu can execute 34-bit arithmetic operation and 24-bit arithmetic logical operation as follows. * 34-bit arithmetic operation * 24-bit arithmetic logical operation - : a-b $ : or + << < 1 | | /20, /18, /16 : a+b : b through : b through + 1 : the absolute value : round & # ! 1- 1+ : and : exclusive-or : not : a-1 : a+1 alu outputs three flags mentioned below, holds the last flag's state at alu-nop. * sgf: this flag shows msb(+4 bits) of alu. sgf flag shows "0" when the result is zero or positive, and shows "1" when the result is negative. * ovf: this flag shows the overflow(exceeding the 0-th bit) of operated result of alu. when overflow is occurred, it shows "1" else "0". the data is output to dbus as follows at overflow; positive overflow: 7fffff(hex) , negative overflow: 800000(hex). in addition, when the data exceed the overflow margin on the way of calculation, this flag is held on "1", output the above data to dbus. * zrf: this flag shows "1" when the result of 24-bit(0 ~ -23) calculation at alu is "0". the 20,18 and 16-bit rounding is prepared. 20-bit rounding execute the addition of "1" to -20th bit( if lsb = all "0" then +0), and execute half-adjust. in the same way, 18-,16-bit rounding add "1" to -18th, -16th bit respectively. the through +1 adds "1" to -24th bit, for the calculation data to be obtained as data rounded to 24-bit in advance, then the execution step for rounding can be omitted. the location of addition point of "1" for 20-bit rounding is shown below. "<1" (b through +1) adds "1" to -25th bit of the input data. in the case that the calculated data is output on dbus, the data is rounded off to 24bits. ,op,cr*dr, ,,,, , ; ,op,cr*dr, ,,,, , ; ,op,cr*dr,idr0=sh0 <1 ,,,, , ; ,op, ,idr0=sh0 + ldr0 ,,,, , ; ,op, ,idr0=sh0 + ldr0 ,,,, , ; ,op, , ,,,, , ; ,op, , ,,,,odr0, ;odr0 is the rounded value of calculated data asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 36 - in each command of alu, input data is processed as follows. command a input b input of zf sf ov alu function nop << <1 + - 1- 1+ | | /20 /18 /16 $ & # ! all "0" -24bits+1,all"0" a a a a a a a,+1 ~ +4bits="0" a,+1 ~ +4bits="0" a,+1 ~ +4bits="0" inversion b b b inversion+1 +4 ~ -23bits="1" -24 ~ -29bits="0" -23bits+1, all "0" all "0" -20bits+1, all"0" -18bits+1, all"0" -16bits+1, all"0" b b b all "0" not change { { { { { { { { { { { { { { { { { { { re { { { re { { { { { { { { { { { { { { { { { re { re { re { re + + + + + + positive: + negative: invertion + 1 + or and exor not { : flag is effective. : don't care. re: reset of overflow register about the timing of alu, the input of b register actions always, but when alu is nop, the value of acc and flag are not changed. it becomes possible to output the result to dbus 2 steps later . asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 37 - 5) division the divider is equipped with a circuit independently. the condition and format of data are as follows. input data: a= dividient (16-bit) : b= divisor (16-bit) output data: q= quotient (16-bit) condition: 0 asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 39 - ? ? ? ? coefficient ram(cram) this is a ram to store coefficient data for such as digital filter, and can be written the data through cbus/dbus. 3 ways are prepared for writing. the first way is to be loaded from such as microcomputer at reset of this lsi. the second way is to write the 16 data written on microcomputer buffer at running state. the last way is writing from dbus, that is controlled by appointing at dst field. output can be done to multiplier directly or to dbus(lower 8 bits are "0" ). the capacity of memory is 256 word 16-bit. two pointers are prepared. cp0 is reset to the address"0(hex)" and cp1 is reset to "80(hex)" every sampling cycle, and appointment of pointer is set to cp0. the address is able to increment(+1) and to decrement(-1). by load command, it is able to load the dbus data directly as pointer value. cpc command not only change the pointer but also does increment of the pointer change from. for example, in the case of changing the pointer from cp0 to cp1, the change cp0 ? cp1 and increment of address of cp0 are done. the timing is shown below. cpc: pointer change(cp0 ? cp1, cp0+1 ; cp1 ? cp0, cp1+1) cpu: increment of address(+1) cpd: decrement of address(-1) cram: output the data to dbus @cp0: load the data to cram-cp0 pointer (for address) @cp1: load the data to cram-cp1 pointer (for address) @cram: write dbus data it is explained below how those timing go in actual program. ,op, ,,cpu,,, , ;be able to output to dbus and multiplier(cr) 2 steps after ,op, ,, ,,, , ; ,op,cr*dr ,,cpu,,,cram, ; ,op, ,, ,,,tmp0 , @cram ;write the data of tmp0 to the address made 1step before by cpu ,op,cr*dr ,, ,,, , ;output the data written 1step before by @cram to cr and dbus ,op, ,,cpc,,, , ; ,op, ,, ,,, , ; ,op, ,, ,,, , ;output the data of pointer changed 2 steps before by crc ,op, ,, ,,, , ;operate with the changed pointer until next cpc is executed asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 40 - ? ? ? ? data ram(dram) data ram is written through the dbus, and is read on multiplier and dbus directly. the capacity of memory is 128 word 24 bit, and two memory pointers are prepared. the pointers of dp0 and dp1 are used after setting to command register from outside before starting. the two method of addressing are prepared, the linear-addressing method which starts with dp0:00h and dp1: 40h, and the ring-addressing method which increases start address for every sampling cycle. when this ring-addressing is chosen, the address is added "1" for every sampling (start of dp0 address:00 ? 01 ? 02 ? 03 ? 04 ?? ). the starting pointer appointment for every sampling cycle is chosen to dp0. the address is able to increment(+1,+2,+3) and to decrement(-1,-2,-3). by load command, it is able to load the dbus data directly as pointer value. on using this load command, or loading dbus data to pointer, the value(loaded value + starting address at ring addressing method, loaded value at linear-addressing method) is loaded to pointer. dpc command executes the change of pointer, at the same time the increment of changed pointer. for example , when the pointer is changed from dp0 to dp1, not only the change of dp0 ? dp1 but also the increment of address of dp0 are done. the timing of it is shown below. dpc: change pointer(dp0 ? dp1,dp0+1 ; dp1 ? dp0,dp1+1) du1: address+1 dd1: address-1 du2: address+2 dd2: address-2 du3: address+3 dd3: address-3 dram: output the data to dbus(at the same time to selector of multiplier) @dp0: load the dbus data to dram-cp0 pointer @dp1: load dbus data to dram-cp1 pointer @dram: write dbus data asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 41 - it is explained below how the timing of previous page is go in actual program. ,op, ,,,du1,, , ;be able to output for dbus and multiplier(dr) 2 steps after. ,op, ,,, ,, , ; ,op,cr*dr ,,,du1,,dram, ; ,op, ,,, ,,tmp0 ,@dram ;write the value of tmp0 to the address made 1 step before by du1 ,op,cr*dr ,,, ,, , ;write the data written 1 step before by @dram to dr and dbus. ,op, ,,,dpc,, , ; ,op, ,,, ,, , ; ,op, ,,, ,, , ;output the data of pointer changed 2 steps before by dpc. ,op, ,,, ,, , ;operation with changed pointer until the next dpc is executed ? ? ? ? external ram control unit this unit controls the creation of write/read address, the ram controlling signal and the receiving/transferring of 16- bit delay data. 32k,128k 8-bit memories are used for sram and pseudo sram, both or one of 64k and 256k 4-bit memories are used for dram. addresses are received from ofram(40word 16bit) data or inner calculation data, i.e. dbus data. the writing for external memory is done from small address number (00 ? 01 ? 02 ? 03 ?? ) with ring address method. in the case of using ofram, the relative address is read from ofram in order of execution, and the real address is calculated. so it needs to write the address data to ofram in order of execution. each external memory access requires 5 cycles of step dsp instruction at sram,p-sram(256k), and 6 cycles at dram,p-sram(1m). writing of data to ofram is loaded from microcomputer or other unit at reset of this lsi. at running state of lsi, if first address of c hanging data is appointed, 16 data can be automatically changed at maximum in order of set address. when all data is changed, this command is automatically canceled . at the case of using cram or internal calculation data(set the address by @dadr), after 2 cycles from @dadr command execution, the execution of read/write command becomes be possible, on this time ofram does not read next data. the maximum access number of times of memory are 76 for sram and pseudo sram(256k) at 384fs, 51 at 256fs(dram, pseudo sram(1m): 64/384fs, 42/256fs), and access time of usable memory is due to input frequency of master clock(xti) and sort of ram for use, refer to switching features described in 18 - 19 page. the timings are shown in fig.1 for external ram and sram, fig.2, 3 for pseudo 256k-sram at using auto-refresh and static column mode read/write cycle, fig.2 and 4 for pseudo 1m-sram at using auto-refresh, read cycle and write cycle (oe clock), fig.5,6 for dram at using cas before ras refresh cycle and page mode read/write cycle. * real address = ofram data + sampling frequency after run = calculation data + sampling frequency after run * relation of write/read address appointed address: 2000h(write) - when the appointment of writing is not exist between these address, delay data of 2000h(write) is read. appointed address: 1000h(read) delay time of these above = (write address-read address) ( 1/fs ) (2000h-1000h) (1/44100) = 92.9msec asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 42 - asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 43 - asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 44 - the controlling of reading/writing are executed by micro code and have functions as follows.
asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 45 - ? ? ? ? dbus(data bus) when output data to dbus is less than 24 bits, the "0" data is supplemented from lsb side. except @iorl command, all input from dbus is taken out the needed data length from msb side. the @iorl inputs lower 8 bits of dbus data. when src field is non or reset state, dbus is set to "l". ? ? ? ? sequence control unit it consists of 384word 32-bit pram(sram), micro program sequencer, 5-bit loop counter, 24-bit bus inter- connection, 8-bit return address register and 8-bit external condition register(ifcon). the writing data to pram, which stores 32-bit horizontal macro command, is loaded at reset of dsp unit by such as microcomputer. by this 32- bit horizontal micro command, the command is read at calculation command, and multiplication, addition, subtraction and data transfer are operated in parallel. the micro program sequencer consists of 9-bit program counter, 1 level stack register, pipeline instruction register and instruction decoder, loop, cal, jmp, end, conditional jmp, external conditional jump and load are executed. the stack is 9-bit and 1 level, and stores the return address when subroutine call command is executed. by using this subroutine and loop, although program capacity is 384 word, can be done 574 steps of operation at maximum when master clock is 576fs (sampling frequency is 32khz only). using this feature, the loop command is convenience for reading/writing of external ram. as the stack is 1 level, it is not able to make call/loop command in the call/loop sentence. but conditional jump is able to use in subroutine. when you make the program in that the jump is not return to the return address in call sentence, akm can not guarantee how does this dsp's action. this is same in loop command. at using that, it can not return to the address stacked at call command. the bus inter-connection between pbus and dbus realizes that the 24-bit data is done the literal load to each register on dbus by instruction. all sequence commands are 1 word commands(32-bit), and the time taken from the output of program counter to the end of command execution is different in each command, but most of this is taken 2 ~ 3 machine cycles. the timing of each instructions are shown below. , jump the timing of jump is shown in the figure below. as the figure shows, 1 machine cycle of nop is inserted before jumping from the address of jump command to appointed address. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 46 - , conditional jump the conditional jump is shown in the figure below. by this command, condition flag(sgf, ovf, zrf of alu) is judged before jump, and if it is satisfied then the address of jump destination is set. then 1 machine cycle of nop is inserted similar to jump. and if it is not satisfied then nop is not inserted, and next address command is executed. the list of conditional jump is shown below. condition alu(a-b) jle : sgf=1 or zrf=1 ; a b jls : sgf=1 jge : sgf=0 jgr : sgf=0 and zrf=0 jzr : zrf=1 jnz : zrf=0 ; a < b ; a 3 b ; a > b ; a = b ; a 1 b jov : ovf=1 jno : ovf=0 asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 47 - , external conditional jump (jx) the timing of external conditional jump is shown as follows. this command inputs the jump condition from outside of lsi to 8-bit conditional jump register. when one of "1" of each bits of it and external conditional register is coincident, the jump is executed. if it is satisfied, the address of jump destination is set. then one machine cycle of nop is inserted similar to jump. and if the condition is not satisfied, nop is not inserted, next address command is executed. the data is set to conditional jump register at rising edge of lrck in motion or reset. , subroutine call (cl) the timing of subroutine call is shown as follows. this command stacks next address before address of call destination, nop is inserted. the preparation for pushing the stacked address is done on return address, and stack address is executed after return address. then nop is not inserted. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 48 - , load command (ld) the timing of load command is shown in the figure below. this command loads the data to objective register through the bus inter-connection and dbus. , end command (ed) the timing of end command is shown in the figure below. this command inserts nop until the rising edge of lrck. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 49 - , loop command the timing of loop command is shown in the figure below. this command operates the programs from next command of the appointed sequence command for loop to the address appointed to return register loop times(maximum 31(1fh) times) over. nop is not inserted at each the return. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 50 - ? ? ? ? input/output function dsp unit of AK7712a has 4 channels of digital input port and 6 channels of digital output port. 2 channels of input ports (sdin2) can be connected to internal adc, 2 channels of output ports (sdout2) can be connected to internal dac1. and another 2 channels of output ports(sdout3) can be connected to internal dac2. the command related to these above is as follows. inl1(dinl): sdin1-lch ? dbus (connect sdin1 ) inr1(dinr): sdin1-rch ? dbus (connect sdin1 ) inl2(adcl): sdin2-lch ? dbus (connect sdin2 ) inr2(adcr): sdin2-rch ? dbus (connect sdin2 ) @otl1(@dotl): dbus ? sdout1-lch register (connect sdout1 ) @otr1(@dotr): dbus ? sdout1-rch register (connect sdout1 ) @otl2(@dal1): dbus ? sdout2-lch register (connect sdout2 ) @otr2(@dar1): dbus ? sdout2-rch register (connect sdout2 ) @otl3(@dal2): dbus ? sdout3-lch register (connect sdout3 ) @otr3(@dar2): dbus ? sdout3-rch register (connect sdout3 ) 1) digital serial input the AK7712 provides 4 channels of digital serial input unit, and each interface format is as follows. this appointment is done at control register. sdin1: msb justified 24/16-bit, lsb justified 16-bit sdin2: msb justified 20/16-bit the data which is input from sdin1(sdin2) is distributed to each register dinl dinr(adcl adcr) at each rising and falling edge of lrck, and these data are output to dbus 1 sampling cycle after. according to each data length, the data is supplemented by "0" to lower bit, and is output to dbus following src field. 2) digital serial output the AK7712 provides 6 channels of digital serial input unit, and each interface format is mentioned below. this appointment is done at control register. sdout1: msb justified 24/16-bit, lsb justified 16-bit sdout2: msb justified 20/16-bit data is loaded to register by src field. msb justified interface output the data taken 1 cycle before. at the rising edge of lrck both data of lch and rch are set to parallel/serial transformation register from upper bit of dbus. in the case above, it can not be guaranteed that the output command of last 4 steps of execution step in program are output by the timing mentioned below. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 51 - ? ? ? ? serial data interface the clocks which are needed are xti, lrck(fs) and bclk( 32fs,48fs,64fs) at slave mode, and only xti at master mode. about the set-up for each format, please refer the section of control register. at master mode,the clock needed is only xti. once input the xti then lrck(fs) and bclk(64fs) are output. the input data is synchronized with " - " of bclk. the output data is synchronized with " "of bclk.. 1.sdin1, sdout1 1) master mode (64fs) sdin1 ( input ) control register setting c17, c16 c15, c14 16bit msb justified 0 , 0 0 , 0 24bit msb justified 0 , 0 0 , 1 16bit lsb justified 0 , 0 1 , 0 24bit lsb justified 0 , 0 1 , 1 fig.7 sdin1 master mode input format sdout1 ( output ) control register setting c17, c16 c13, c12 16bit msb justified 0 , 0 0 , 0 24bit msb justified 0 , 0 0 , 1 16bit lsb justified 0 , 0 1 , 0 fig.8 sdout1 master mode output format asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 52 - 2) slave mode [64fs] sdin1 ( input ) control register setting c17, c16 c15, c14 16bit msb justified 0 , 0 0 , 0 24bit msb justified 0 , 0 0 , 1 16bit lsb justified 0 , 0 1 , 0 24bit lsb justified 0 , 0 1 , 1 fig.9 sdin1 slave mode input format ( 64 fs ) sdout1 ( output ) control register setting c17, c16 c13, c12 16bit msb justified 0 , 0 0 , 0 24bit msb justified 0 , 0 0 , 1 16bit lsb justified 0 , 0 1 , 0 fig.10 sdout1 slave mode output format ( 64fs ) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 53 - [48fs] sdin1 ( input ) control register setting c17, c16 c15, c14 16bit msb justified 1 , 0 0 , 0 24bit msb justified 1 , 0 0 , 1 16bit lsb justified 1 , 0 1 , 0 fig.11 sdin1 slave mode input format ( 48 fs ) sdout1 ( output ) control register setting c17, c16 c13, c12 16bit msb justified 1 , 0 0 , 0 24bit msb justified 1 , 0 0 , 1 16bit lsb justified 1 , 0 1 , 0 fig.12 sdout1 slave mode output format ( 48fs ) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 54 - [32fs] sdin1 ( input ) control register setting c17, c16 c15, c14 16bit msb justified 0 , 1 0 , 0 fig.13 sdin1 slave mode input format ( 32 fs ) sdout1 ( output ) control register setting c17, c16 c13, c12 16bit msb justified 0 , 1 0 , 0 fig.14 sdout1 slave mode output format ( 32fs ) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 55 - 2.sdad, sdin2 1) master mode ( 64fs ) sdad ( output ) 20bit msb justified fig.15 sdad master mode output format sdin2 ( input ) control register setting c17, c16 c11 20bit msb justified 0 , 0 0 16bit msb justified 0 , 0 1 fig.16 sdin2 master mode input format asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 56 - 2) slave mode [64fs] sdad ( output ) 20bit msb justified fig.17 sdad slave mode output format ( 64fs ) sdin2 ( input ) control register setting c17, c16 c11 20bit msb justified 0 , 0 0 16bit msb justified 0 , 0 1 fig.18 sdin2 slave mode input format ( 64fs ) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 57 - [48fs] sdad ( output ) 20bit msb justified fig.19 sdad slave mode output format ( 48fs ) sdin2 ( input ) control register setting c17, c16 c11 20bit msb justified 1 , 0 0 16bit msb justified 1 , 0 1 fig.20 sdin2 slave mode input format ( 48fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 58 - [32fs] sdad ( output ) 16bit msb justified fig.21 sdad slave mode output format ( 32fs ) sdin2 ( input ) control register setting c17, c16 c11 16bit msb justified 0 , 1 1 fig.22 sdin2 slave mode input format ( 32fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 59 - 3.sdout2, sdda 1) master mode ( 64fs ) sdout2 ( output ) control register setting c17, c16 c10 20bit msb justified 0 , 0 0 16bit msb justified 0 , 0 1 fig.23 sdout2 master mode output format sdda ( input ) control register setting c17, c16 20bit msb justified 0 , 0 fig.24 sdda master mode input format asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 60 - 2) slave mode ( 64fs ) [64fs] sdout2 ( output ) control register setting c17, c16 c10 20bit msb justified 0 , 0 0 16bit msb justified 0 , 0 1 fig.25 sdout2 slave mode output format ( 64fs ) sdda ( input ) control register setting c17, c16 20bit msb justified 0 , 0 fig.26 sdda slave mode input format ( 64fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 61 - [48fs] sdout2 ( output ) control register setting c17, c16 c10 20bit msb justified 1 , 0 0 16bit msb justified 1 , 0 1 fig.27 sdout2 slave mode output format ( 48fs ) sdda ( input ) control register setting c17, c16 20bit msb justified 1 , 0 fig.28 sdda slave mode input format ( 48fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 62 - [32fs] sdout2 ( output ) control register setting c17, c16 c10 16bit msb justified 0 , 1 1 fig.29 sdout2 slave mode output format ( 32fs ) sdda ( input ) control register setting c17, c16 20bit msb justified 0 , 1 fig.30 sdda slave mode input format ( 32fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 63 - 4.sdout3, sdda2 1) master mode ( 64fs ) sdout3 ( output ) control register setting c17, c16 20bit msb justified 0 , 0 fig.31 sdout3 master mode output format sdda2 ( input ) control register setting c17, c16 20bit msb justified 0 , 0 fig.32 sdda2 master mode input format asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 64 - 2) slave mode ( 64fs ) [64fs] sdout3 ( output ) control register setting c17, c16 20bit msb justified 0 , 0 fig.33 sdout3 slave mode output format ( 64fs ) sdda2 ( input ) control register setting c17, c16 20bit msb justified 0 , 0 fig.34 sdda2 slave mode input format ( 64fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 65 - [48fs] sdout3 ( output ) control register setting c17, c16 20bit msb justified 1 , 0 fig.35 sdout3 slave mode output format ( 48fs ) sdda2 ( input ) control register setting c17, c16 20bit msb justified 1 , 0 fig.36 sdda2 slave mode input format ( 48fs ) asahi kasei [AK7712a-vt] 0810-e-02 1997/12 - 66 - [32fs] sdout3 ( output ) control register setting c17, c16 16bit msb justified 0 , 1 fig.37 sdout3 slave mode output format ( 32fs ) sdda2 ( input ) control register setting c17, c16 16bit msb justified 0 , 1 fig.38 sdda2 slave mode input format ( 32fs ) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 67 - ? ? ? ? microcomputer interface microcomputer interface is operated with 7 control signals, which are si(serial data input), so(serial data output), sclk (serial data input clock), wrdy(write ready), cs(chip select), wrq(write request) and drdy(data ready). all the data is done serial i/o with msb first. the operating contents are transferred as 8-bit command data shown below, and the appointed operations are executed. write program ram [rspw](at reset) : code(1 1 0 0 0 0 0 0) write code for external conditional jump [jcon](at run,reset) : code(1 1 0 0 0 1 0 0) write coefficient ram [rscw](at reset) : code(1 0 1 0 0 0 0 0) write coefficient ram [rncw](at run) : code(1 0 1 0 0 1 0 0) write offset ram [rsow](at reset) : code(1 0 0 1 0 0 0 0) write offset ram [rnow](at run) : code(1 0 0 1 0 1 0 0) prepare to write cram/offram [rnbw](at run) : code(1 0 0 0 1 0 0 0) write control register [conw](at reset) : code(0 0 0 0 0 1 1 0) 1) writing program ram the writing to program ram is executed with 7bytes/set at reset. if all the data is transferred, wrdy pin becomes "l", and if the writing to pram is finished, it becomes "h" and next data becomes be able to be input. in case of writing data with the continuos address, input the data directly(command code and address are not needed). if it's discontinuous, set wrq pin "h" ? "l", and input in the order of command code, address and data. 1 { command code (1 1 0 0 0 0 0 0) 2 { address(upper) (0 0 0 0 0 0 0 a8) 2 { address(lower) (a7 a0) 3 { data (d31 d24) 4 { data (d23 d16) 5 { data (d15 d8) 6 { data (d7 d0) 2) writing coefficient ram the writing coefficient ram(at reset) is executed with 4bytes/set data. if all the data is transferred, wrdy pin becomes "l", and if the writing to cram is finished, it becomes "h" and next data becomes be able to be input. in case of writing data with the continuos address, input the data directly. if it's discontinuous, set wrq pin "h" ? "l", and input in the order of command code, address and data. 1 { command code (1 0 1 0 0 0 0 0) 2 { address (a7 a0) 3 { data (d15 d8) 4 { data (d7 d0) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 68 - 3) writing offset ram the writing to program ram is executed with 4bytes/set at reset. if all the data is transferred, wrdy pin becomes "l", and if the writing to offram is finished, it becomes "h" and next data becomes be able to be input. in case of writing data with the continuos address, input the data directly. if it's discontinuous, set wrq pin "h" ? "l", and input in the order of command code, address and data. 1 { command code (1 0 0 1 0 0 0 0) 2 { address (0 a6 a0) 3 { data (d15 d8) 4 { data (d7 d0) 4) preparation of rewriting coefficient offset ram(run state) and rewriting this is used to rewrite the coefficient offset ram when program is running. after input of command code, the data, which is wanted to rewrite with the continuos address, can be able to input up to 16. secondary, if the write command code and first address for rewrite are input then contents of ram is rewritten every appointment of the rewritten ram address. for example, when 5 data are rewritten by address"10" of coefficient ram, it's executed as follows. coefficient ram execution address 7 8 9 10 11 13 16 11 12 13 14 15 rewrite execution position { { - { { { address"13" is not rewritten until address"12" is rewr itten. * rewrite preparation 1 { command code (1 0 0 0 1 0 0 0) 2 { data (d15 d8) 3 { data (d7 d0) * rewrite 1 { command code:cram (1 0 1 0 0 1 0 0) :ofram (1 0 0 1 0 1 0 0) 2 { first address (a7 a0) asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 69 - 5) writing code for external conditional jump the writing code for external conditional jump is executed with 2byte/set. it is able to input at both of reset run, and the input data is set to register at rising of lrck. when all the data is transferred, wrdy becomes "l", and if the writing is finished, it becomes "h". the external conditional code is 8-bit, and if any one or more of bits of this code is coincident with "1" of each code of ifcon field, the jump command is executed. when the data is written at reset state, it can be executed only after all the data transferred or before cancel. please set wrq to "h" after 150nsec or more after rising of lrck after cancellation of reset at write on reset state. < data transfer procedure> 1 { command code (1 1 0 0 0 1 0 0) 2 { code data (d7 d0) 6) writing control register the writing control register(at reset) is executed with 4bytes/set. when all the data is transferred, wrdy becomes "h", and if the writing is finished, it becomes "h". 1 { command code (0 0 0 0 0 1 1 0) 2 { control data (c23 c16) 3 { controla data (c15 c8) 4 { control data (c7 c0) the register, which is controlling the action mode of this lsi, is consists of 24 bits. the function of each bit is shown in table 1 as follows. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 70 - [ table 1 ] bit name function c23 external ram data length selection 1: 4-bit, 0: 8-bit(default value) external ram selection (c22,c21,c20) = (0,0,0): sram (default value) c22 c21 c20 (0,1,0): pseudo sram(static column mode) (0,1,1): pseudo sram(normal mode) (1,0,0): dram 256k (1,0,1): dram 1m(use as 512k) c19 data reset function selection after reset 1: not use, 0: use(default value) addressing method selection of dram 0: ring addressing (default value) c18 1: linear addressing bclk selection (c17,c16) = (0,0): 64fs(default value) effective only slave mode c17 c16 (0,1): 32fs (1,0): 48fs sdin1 interface selection (c15,c14) = (0,0): msb justified 16-bit 32/48/64fs c15 c14 (0,1): msb justified 24-bit 48/64fs (1,0): lsb justified 16-bit 48/64fs (1,1): lsb justified 24-bit 64fs sdout1 interface selection (c13,c12) = (0,0): msb justified 16-bit 32/48/64fs c13 c12 (0,1): msb justified 24-bit 48/64fs (1,0): lsb justified 16-bit 48/64fs (0,0): (default value) sdin2 interface selection 0: msb justified 20-bit 48/64fs c11 1: msb justified 16-bit 32/48/64fs 0: (default value) sdout2 interface selection 0: msb justified 20-bit 48/64fs c10 1: msb justified 16-bit 32/48/64fs 0: (default value) reserve/ test (c9,c8) = (0,0): (default value) note 1) c9 c8 c7 reserve/ test 0: (defaul value) note 1) c6 adc hpf selection 1: not use, 0: use(default value) c5 pink noise generation 0: (default value) 1: use c4 reserve/ test 0: (default value) note 1) master clock selection (c3,c2) = (0,1): (default value) xti dsp fs max clock (0,0): 384fs 384fs 48/44.1/32khz 18.432mhz (0,1): 256 256 48/44.1/32 12.288mhz c3 c2 (1,0): 512 (1,1): 576 512 576 32 32 16.384mhz 18.432mhz c1 reserve/ test 0: (default value) note 1) c0 reserve/ test 0: (default value) note 1) * other codes except for this table are reserved. do not use these reserved codes. note 1) do not change the reserve/ test as it may be used for test. it may become the cause of irregular action. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 71 - 7) timing with microcomputer in case of transferring data from microcomputer, the command data can be input on condition that the wrq is set to "h", the command register is reset and wrq is set to "l". cs must be set to "l" in case of receiving/ transferring data from/to this lsi. if cs is set to "h", then so and wrdy become "hi-z" state and can not receive/transform data. the timing of data load at reset(rst ="l", pd ="hi") is shown in fig.38 and 39. if the transferring data is finished then wrdy signal becomes "l", and if down load is finished then it return to "h". the motion transferring next data is suppressed in that period(wrdy= "l"). since the period has short length about 2 cycles of master clock, if sclk is slow enough then monitoring of wrdy is not needed. fig.38 input of continuos address data to pram,cram and ofram fig.39 input of discontinuos address data to pram,cram and ofram asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 72 - in case of changing the data of cram and ofram data at run state, execute preparation of writing data at run state(in this case, address is unnecessary and rst is "h") by writing to buffer memory similar to fig.11. secondary, set wrq to "l" and if input of command code and address is finished then set wrq to "h". if the preparation for rewrite is finished inside, wrdy signal becomes "l", and rewrite command is executed from rising of lrck. and if rewriting is finished, wrdy becomes to "h". these timing is shown in fig.41. fig.41 data rewrite timing at run state asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 73 - the external conditional jump can be written at reset/run state. these timing are shown in fig.42 and 43. at reset state, the "l" ? "h" in wrq must be executed after 3mck from "l" ? "h" in rst. but, at run state, "l" ? "h" in wrq can be executed at once after transferring jump condition. wrdy signal becomes "h" ? "l" after transferring jump condition, and 2 cycles after setting rst/wrq to "h", becomes "l" ? "h" at rising edge of lrck. as similar to above, data transferring is suppressed in the period of wrdy="l". fig.42 write timing external conditional jump at reset fig.43 write timing of external conditional jump at run time asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 74 - so can output the data on dbus of this lsi. by appointing @micr at dst field, the data is set, and drdy becomes to "h", and the data is put synchronizing with falling edge of sclk. if once cs is changed to "h", drdy becomes to "l", and wait the next command. if once drdy becomes to "h", the data of first @micr command after drdy="h" is held and other command is not received while cs is held "l".in case of output from so, set wrq to "h", and cs to "l". fig.44 output timing of so * attentions concerning of control signal for micro computer interface control signal for micro computer interface(cs, rst, wrq should be allowed to change when sclk is in "h" state. * so output is maximum 24bit data. after obtaining the indispensable number of data(less than 24), the subsequent data can be possible to output when cs is in "h" state. ? high-pass filter AK7712a has digital high-pass filter(hpf) for dc offset cancel. hpf is active when control register c6 is "0". the cut-off frequency of hpf is about 1hz(fs=48khz). if c6 is set to "1" then hpf becomes unavailable. in that case, AK7712a has dc offset of a few millivolts. ? zero detection function in the case that "0" of both channels of input data repeats 8192 times, dzf becomes "h". after that, if input data becomes not "0" then dzf becomes "l" at once. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 75 - ? system clock the system clock of AK7712a is xti at master mode. and these are xti, lrck(fs) and bclk at slave mode. in case of using slave mode, xti and lrck must be synchronized but those phases do not need to be muched. internal clock circuit master clock can be obtained by quartz oscillator connected between xti pin and xto pin, or by openning xto pin and inputting the external clock to xti pin. the frequencies of each clocks needed for standard audio rate is shown in the table below. example of quartz oscillator connection lrck (fs) (khz) xti (fs) (mhz) 256 8.1920 384 12.2880 32.0 512 16.3840 256 11.2896 44.1 384 16.9344 256 12.2880 48.0 384 18.4320 asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 76 - ? notes on use 1) in the case that external clock is not supplied at run state at run state(pd="h"), do not stop each external clock. xti at master mode, and xti,bclk and lrck at slave mode are needed. if these clocks are not supplied, the circuit is overloaded and the action becomes abnormal since the dynamic logic is used inside. 2) in the case that system clock frequency is changed at slave mode, the inside timing must be synchronized with lrck supplied from outside. this synchronization is done by reset inside master counter. this reset is done only one time at lrck" - " after rst " - ". after that, digital filter operates only with inside master clock, writes data to output register. in the case that synchronism breaks down by changing each system clock frequency, the output data may become anomaly for overlap of write timing to output register and read timing by lrck. so, change clock with rst "l"(pdad,pdda="l"), and reset both built-in adc,dac. but, the phase shift between lrck and inside timing is out of the range from 1/16 to -1/16 of input sampling cycle(1/fs), the adjustment of phase of inside timing is done synchronized with lrck" - "(same as reset state). asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 77 - ? ? ? ? reset control 1) system reset during power-up, please reset by setting both pd and rst pin "l" to "h". the reset is cancelled at xti " - ". then, the inside timing becomes to synchronize with lrck" - ", and the inside lrck becomes to action since 4lrck after, and dsp unit becomes to action. 2) powerdown-reset control the reset is controlled with 2 pins of system reset(rst)and power down(pd). it is also able to control the state of adc/dac by using pdad/pdda pins in support. the setting of "pd:l, rst:l" makes all the circuit reset and mos resistance of quartz oscillator off. in this state, by stopping xti, bclk and lrck, power down state is realized(the leak is checked with this state at test). at "pd:l, rst:l", since mos resistance of quartz oscillator is also off, output from clko and xto can not be guaranteed. "pd:l, rst:l" is used at power on, or at setting to power down state. if "pd:h, rst:l" is set, each register of dsp unit is reset(control register is not reset), and pram, dram and ofram become write enable state. in that case, both of ad unit and da unit become reset( power down) state(when pdad and pdda are "l"). the reset( power down) state is cancelled at first " - " of xti after setting rst to "h". in that case, dac output is done after 2ts cycles, but adc takes 516ts cycles for initialize, then output data becomes "0". (ts = 1/fs) by pdad/pdda, the control of reset state(power down) for ad/da unit can be separated to the control of reset for dsp unit. usually both of pdad and pdda are used with "l". but in the case that dsp is reset and pram,dram and ofram are rewritten, not to make adc and dac power down state, please set pdad and pdda to "h" after power on. pd "l" "h" "h" "h" "h" "h" rst "l" "l" "l" "l" "l" "h" pdad - "l" "l" "h" "h" - pdda - "l" "h" "l" "h" - ad pd ? ? run run run da pd ? run ? run run (-: don't care, pd: power down, run: run state, ? : can not run) the format is shown in the table . in the case of writing data to control register, set pdad and pdda to "l". to make the change of pdad and pdda, set rst to "l". asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 78 - 3)action of dsp unit, at reset this lsi has two kinds of reset; "reset(rst)" and "power down(pd)". if rst is set to "l"(pd ="h"), each register is reset, and pram,cram and ofram become write enable state. if rst is set to "h"(pd="h"), the reset is cancelled, and the external ram clear("0" data write) and the write data"0" to internal dram are executed from the rising edge of lrck. this period takes 2260*1/fs [sec](fs: sampling frequency). in periods of reset and of write "0"data to dram, input/output data is operates as "0". in these periods, dzf is kept "h". these period take 51.3msec at 44.1khz(384fs). to be disable this function, set control register c19 to "1".this timing is shown in fig.45. fig.45 timing at reset and after cancellation of reset if both of rst and pd are set to "l", this lsi becomes power down state, so the control register is also reset to default state. after cancellation, it actions same above. to change the control register or program, set pd to "h", load data, set rst to "h". fig.46 timing at power down and after cancellation of reset asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 79 - system design connection : asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 80 - the connection to external ram is as follows. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 81 - asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 82 - ? periphery circuit 1. ground and power supply in AK7712a, to keep the coupling of digital noise in minimum, avdd and dvdd are done the decoupling independently.avdd,avb and dvb are supplied with analog power supply of system. avb and dvb are connected each other by ic-substrate, and have a resistance of several ohms. if avdd, avb, dvb and dvdd are supplied by another power supply, avdd,avb and dvb must be powered at the same time as dvdd ,or avdd,avb,dvb must be powered at first. in the general way, separate both of power supply and ground between analog and digital, and connect near power supply on pc board. the decoupling capacitor, especially ceramic capacitor of small capacity must be connected near AK7712a. caution: keep avdd,avb,dvb 3 dvdd-0.3v, or the over current causes latch-up and this ic may fall into destruction. 2. standard voltage the difference of input voltage between vradh pin and vradl pin decide the full-scale of analog input, and the difference of voltage between vrdah pin and vrdal pin decide the full-scale of analog output. usually connect vradh with avdd1, and vrdah with avdd2, and connect the ceramic capacitor of 0.1uf between avss1 and avss2. vcom is used as the common voltage of analog signal. connect electrolytic capacitor about 10 m f and the ceramic capacitor of 0.1uf in parallel between this pin and avss to remove high-frequency noise. especially, the ceramic capacitor must be connected to the pin as near as possible. do not get current from vcom pin. digital signal, especially the clock must be parted as far as possible from vradh,vradl,vrdah,vrdal and vcom pin to avoid the coupling to AK7712a. 3. analog input analog input signal is input to modulator from differential input pin of each channel. the input voltage is differential of ain+ and ain- ( d v ain =(ain+)-(ain-)), and the input range is fs= (vradh-vradl) 0.4 . when vradh=5v and vradl=0v, the input range is 2.0v. the code of output code format is 2's complement. the output code against the input voltage is shown in table 2. output code (sexadecimal digit) input voltage 16-bit 20-bit >(+fs-1.5lsb) 7fff 3ffff -0.5lsb 0000 ffff 00000 7ffff <(-fs+0.5lsb) 8000 80000 table 2. input voltage vs. output code at fs=48khz, AK7712a does sampling the analog input with 3.072mhz. the digital filter removes noise between 30khz and 3.042mhz. but near 3.072mhz, noise is not removed. since almost all audio signal does not have noise near 3.072mhz, so the noise can be reduced enough by simple rc filter. the standard voltage of a/d conversion is input to vradh pin and vradl pin. usually vradh is connected with avdd1 and vradl is connected with avss1. to remove high-frequency noise, connect 10uf electrolytic capacitor and 0.1uf ceramic capacitor in parallel between vradh pin and vradl pin. since the analog power supply voltage of AK7712a is set to +5v, do not input the voltage more than (avdd1)+0.3v or the voltage less than (avss1)-0.3v or the current more than 10ma to analog input pin(ainl,ainr). the over current causes destruction of inner protective circuit, moreover latch-up, and the ic falls into destruction. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 83 - accordingly, in the case that power supply voltage of periphery analog circuit is 15v, then it is needed to protect the analog input pin from the signal which is more than maximum absolute rating. fig.47 example of input buffer circuit(differential input) fig.48 example of input buffer circuit(single-end input) it is also available to input analog signal to AK7712a with single-end. in that case, input the analog signal(in case of usingthe inner standard voltage, the full-scale is 4.0vp-p) to ain-input, and input the bias to ain+input. but, at using single-end input type, 2nd harmonic distortion is pretty big, then the features of s/n+d will be worse than at using differential input (fig.48). 4. analog output the analog output is single-end type, the output range is 2.9vpp(typ) and centered on vcom voltage. outband noise(shaping noise), which is generated by built-in ds modulator, is reduced by built-in switched capacitor filter(scf) and continuous filter(ctf). accordingly, it is not needed to add external filter in usual use. the input code format is 2's complement, and the output is positive full-scale at 7fffh(@16-bit), the negative full-scale at 8000h(@16-bit) and ideally vcom voltage at 0000h(@16-bit). asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 84 - as analog output of this lsi has dc offset of several mv, cut the dc component by capacitor in usual use. fig.49 is a example of external circuit that makes the output double. in this example, output is reversed. fig.49 example of external circuit(gain; 2) 5. connection with digital circuit to minimize the noise caused by digital circuit, connect cmos logic to digital output. the conformable logic families are 4000b, 74hc, 74ac, 74act and 74hct. asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 85 - package ? 100pin lqfp (unit: mm) ? ? ? ? material & lead finish package: epoxy lead-frame: copper lead-finish: soldering plate asahi kasei [AK7712a-vt] 0180-e-02 1997/12 - 86 - marking xxxxaaa data code identifier xxxx: assembly date (number) aaa: lot number (alphabet) important notice z these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. z akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. z it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. |
Price & Availability of AK7712
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |